IPC J STD 027 : 0
Current
The latest, up-to-date edition.
MECHANICAL OUTLINE STANDARD FOR FLIP CHIP AND CHIP SIZE CONFIGURATIONS
Hardcopy
English
02-01-2003
1. SCOPE
1.1 Purpose
1.2 Intent
2 APPLICABLE DOCUMENTS
3 REQUIREMENTS
3.1 Recommended Mechanical Outline for Flip Chip Dice and
Chip Size Packages
3.1.1 Flip Chip Devices
3.1.2 Chip Size Packages
3.1.3 I/O Capability
3.2 Interconnection Bump/Contact Attributes
3.2.1 Functional Types
3.2.2 Ball/Bump/Land Sizes
3.2.3 Ball/Bump/Land Patterns
3.2.4 I/O Drivers on the Periphery
3.2.5 Isolating Sensitive I/Os
3.2.6 Ball/Bump/Land Height Uniformity and Coplanarity
Annex A NORMATIVE TERMINOLOGY
Annex B ACRONYMS
Figures
Tables
Defines mechanical outline requirements for devices supplied in flip chip or Chip Size Package (CSP) formats, including die surface, die terminals, and interconnection balls/bumps/lands to the next level.
| DevelopmentNote |
Included in IPC C 106. (06/2008) Included in IPC C 103 & IPC C 1000. (08/2008)
|
| DocumentType |
Standard
|
| Pages |
96
|
| PublisherName |
Institute of Printed Circuits
|
| Status |
Current
|
| IPC J STD 026 : 0 | SEMICONDUCTOR DESIGN STANDARD FOR FLIP CHIP APPLICATIONS |
| IPC J STD 012 : 0 | IMPLEMENTATION OF FLIP CHIP AND CHIP SCALE TECHNOLOGY |
| IPC E 500 : LATEST | IPC ELECTRONIC DOCUMENT COLLECTION |
| IPC J STD 028 : 0 | PERFORMANCE STANDARD FOR CONSTRUCTION OF FLIP CHIP AND CHIP SCALE BUMPS |
| IPC SM 782 : A1993 AMD 2 1999 | SURFACE MOUNT DESIGN AND LAND PATTERN STANDARD |
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