IEEE/IEC 62530-2011
Current
Current
The latest, up-to-date edition.
IEEE/IEC International Standard - SystemVerilog -- Unified Hardware Design, Specification, and Verification Language
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
05-19-2011
US$544.10
Excluding Tax where applicable
This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language.
| Committee |
Design Automation
|
| DocumentType |
Standard
|
| ISBN |
978-0-7381-6607-0
|
| Pages |
1294
|
| PublisherName |
Institute of Electrical & Electronics Engineers
|
| Status |
Current
|
| Supersedes |
| IEEE 1800-2005 | IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language |
| IEEE 1364-2005 | IEEE Standard for Verilog Hardware Description Language |
| IEEE 1364-2001 | IEEE Standard Verilog Hardware Description Language |
| IEEE 1364-1995 | IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language |
| IEEE 754-2008 REDLINE | IEEE Standard for Floating-Point Arithmetic |
| IEEE 1003.1-2008 | IEEE Standard for Information Technology - Portable Operating System Interface (POSIX(TM)) |
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