IEC 61188-5-1:2002

FOREWORD
1 Scope and object
2 Normative references
3 Terms and definitions
4 Design requirements
   4.1 General
        4.1.1 Classification
        4.1.2 Land pattern determination
   4.2 Dimensioning systems
        4.2.1 Component tolerancing
        4.2.2 Land tolerancing
        4.2.3 Fabrication allowances
        4.2.4 Assembly tolerancing
        4.2.5 Dimension and tolerance analysis
   4.3 Design producibility
        4.3.1 SMT land pattern
        4.3.2 Standard component selection
        4.3.3 Circuit substrate development
        4.3.4 Assembly considerations
        4.3.5 Provision for automated test
        4.3.6 Documentation for SMT
   4.4 Environmental constraint
        4.4.1 Moisture sensitive components
        4.4.2 End-use environment considerations
   4.5 Design rules
        4.5.1 Component spacing
        4.5.2 Single- and double-sided board assembly
        4.5.3 Solder paste stencil
        4.5.4 Component stand-off height for cleaning
        4.5.5 Fiducial marks
        4.5.6 Conductors
        4.5.7 Via guidelines
        4.5.8 Standard fabrication allowances
        4.5.9 Panelization
   4.6 Outer layer finishes
        4.6.1 Solder-mask finishes
        4.6.2 Solder-mask clearances
        4.6.3 Land-pattern finishes
5 Quality and reliability validation
   5.1 Validation techniques
6 Testability
   6.1 Five types of testing
        6.1.1 Bare-board test
        6.1.2 Assembled board test
   6.2 Nodal access
        6.2.1 Test philosophy
        6.2.2 Test strategy for bare boards
   6.3 Full nodal access for assembled board
        6.3.1 In-circuit test accommodation
        6.3.2 Multi-probe testing
   6.4 Limited nodal access
   6.5 No nodal access
   6.6 Clam-shell fixtures impact
   6.7 Printed board test characteristics
        6.7.1 Test land pattern spacing
        6.7.2 Test land size and shape
        6.7.3 Design for test parameters
7 Printed board structure types
   7.1 General considerations
        7.1.1 Categories
        7.1.2 Thermal expansion mismatch
   7.2 Organic base material
   7.3 Non-organic base materials
   7.4 Alternative PB structures
        7.4.1 Supporting-plane PB structures
        7.4.2 High-density PB technology
        7.4.3 Discrete-wire interconnect
        7.4.4 Constraining core structures
        7.4.5 Porcelainized metal (metal core) structures
8 Assembly considerations for surface-mount technology (SMT)
   8.1 SMT assembly process sequence
   8.2 Substrate preparation
        8.2.1 Adhesive application
        8.2.2 Conductive adhesive
        8.2.3 Solder paste application
        8.2.4 Solder preforms
   8.3 Component placement
        8.3.1 Component data transfer
   8.4 Soldering processes
        8.4.1 Wave soldering
        8.4.2 Vapour-phase soldering
        8.4.3 IR reflow
        8.4.4 Hot air/gas convection
        8.4.5 Laser reflow soldering
   8.5 Cleaning
   8.6 Repair/rework
        8.6.1 Re-use of removed components
        8.6.2 Heatsink effects
        8.6.3 Dependence on printed board material type
        8.6.4 Dependence on copper land and conductor layout
        8.6.5 Selection of suitable rework equipment
        8.6.6 Dependence on assembly structure and soldering
              processes
Annex A (informative) Test patterns - Process evaluations
Annex B (informative) Abbreviations
Figures
Tables

Provides information on land pattern geometries used for the surface attachment of electronic components. The intent of the information presented herein is to provide the appropriate size, shape and tolerance of surface-mount land patterns to insure sufficient area for the appropriate solder fillet, and also to allow for inspection, testing, and rework of those solder joints.