IPC J STD 013 : 0
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
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IMPLEMENTATION OF BALL GRID ARRAY AND OTHER HIGH DENSITY TECHNOLOGY
Hardcopy
01-10-2013
English
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1 Scope
1.1 Purpose
1.2 Categorization
1.3 Presentation
1.4 Producibility
2 Technology Overview of Board and Assembly
Requirements
2.1 The Drivers for Component Packaging
2.2 Issues in Component Packaging
2.3 Impact on Interconnecting (Printed Board)
Technology
2.4 Impact on Assembly
2.5 Future Implementation Strategies
3 Component Packages
3.1 Component Identification
3.2 Component Materials
3.3 Heat Dissipation Techniques
3.4 Handling and Storage
4 Package Details
4.1 Area Array Package Description
4.2 BGA Types
4.3 Material Decisions
4.4 Area Array Selection Process
4.5 Peripheral Lead Package Descriptions
4.6 Sockets
5 Interconnecting Structures
5.1 Interconnecting Structure Descriptions
5.2 Material Selection
5.3 Manufacturing Options
5.4 Conductor Routing Methodologies
5.5 Test Methodology
6 Assembly Processes
6.1 Assembly Classification
6.2 Assembly Materials
6.3 Equipment Characteristics
6.4 Package Attachment Process Details
6.5 Assembled Board Test
7 Design for Reliability (DfR)
7.1 Damage Mechanisms and Failure of Solder
Attachments
7.2 Reliability Prediction Modelling
7.3 DfR-Process
7.4 Validation and Qualification Tests
7.5 Screening Procedures
7.6 Reliability Expectations
8 Standardization
8.1 Standards for Development
8.2 Ball Grid Array Development and Performance
Standards
8.3 Standard on Mounting of Substrate Design and
Performance
8.4 Ball Grid Array/Substrate Assembly Design and
Performance Standards
8.5 Standards for Material Performance
9 Future Needs
9.1 Critical Factor: Manufacturing Infrastructure
9.2 Critical Factor: Bump Attachment and Bonding
9.3 Critical Factor: Testing Scenarios
9.4 Total Quality Management and Manufacturing
(TQMM)
Figures
Tables
Outlines the requirements and interactions necessary for Printed Board Assembly processes for interconnecting high performance/high pin count IC packages. Included is information on design principles, material selection, board fabrication, assembly technology, testing strategy, and reliability expectations based on end-use environments.
| DocumentType |
Standard
|
| Pages |
103
|
| PublisherName |
Institute of Printed Circuits
|
| Status |
Superseded
|
| SupersededBy |
| Standards | Relationship |
| IEC PAS 62085:1998 | Identical |
| IPC CM 770 : E | COMPONENT MOUNTING GUIDELINES FOR PRINTED BOARDS |
| IPC J STD 032 : 0 | PERFORMANCE STANDARD FOR BALL GRID ARRAY BALLS |
| IPC J STD 012 : 0 | IMPLEMENTATION OF FLIP CHIP AND CHIP SCALE TECHNOLOGY |
| IPC SM 784 : 0 | GUIDELINES FOR CHIP-ON-BOARD TECHNOLOGY IMPLEMENTATION |
| IPC J STD 026 : 0 | SEMICONDUCTOR DESIGN STANDARD FOR FLIP CHIP APPLICATIONS |
| IEC PAS 62084:1998 | Implementation of flip chip and chip scale technology |
| IPC J STD 012 : 0 | IMPLEMENTATION OF FLIP CHIP AND CHIP SCALE TECHNOLOGY |
| IPC J STD 028 : 0 | PERFORMANCE STANDARD FOR CONSTRUCTION OF FLIP CHIP AND CHIP SCALE BUMPS |
| IPC WP 003 : 1993 | CHIP MOUNTING TECHNOLOGY (CMT) |
| IPC SM 782 : A1993 AMD 2 1999 | SURFACE MOUNT DESIGN AND LAND PATTERN STANDARD |
| IPC M 103 : LATEST | STANDARDS FOR SURFACE MOUNT ASSEMBLIES MANUAL |
| IPC 7095 : C | DESIGN AND ASSEMBLY PROCESS IMPLEMENTATION FOR BGAS |
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