IEEE DRAFT 1076.3 : 1995
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
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VHDL SYNTHESIS PACKAGES
23-07-2013
12-01-2013
1 Overview
1.1 Scope
1.2 Terminology
1.3 Conventions
2 References
3 Definitions
4 Interpretation of the standard logic types
4.1 The STD_ LOGIC 1164 values
4.2 Statically valued expressions
4.3 Interpretation of logic values
5 The STD_ MATCH function
6 Signal edge detection
7 Standard arithmetic packages
7.1 Allowable modifications
7.2 Compatibility with IEEE Std 1076-1987
7.3 The NUMERIC_BIT package
7.4 The NUMERIC_STD package
Annex Notes on the package Function
A.1 General considerations
A.2 Arithmetic operator functions
A.3 Relational operator functions
A.4 Shift functions
A.5 Type conversion fuctions
A.6 Logical operator functions
A.7 The STS-MATCH function
Describes standard practices for synthesizing binary digital electronic circuits from VHDL source code.
| DocumentType |
Draft
|
| PublisherName |
Institute of Electrical & Electronics Engineers
|
| Status |
Superseded
|
| SupersededBy |
| IEEE 1164-1993 | IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) |
| IEEE 1076-2008 REDLINE | IEEE Standard VHDL Language Reference Manual |
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