IEEE 1149.10-2017
Current
The latest, up-to-date edition.
IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture
Hardcopy , PDF
English
28-07-2017
1. Overview
2. Normative references
3. Definitions, abbreviations, acronyms, and
special terms
4. High-speed test access port (HSTAP)
5. Packet encoder/decoder and distribution
architecture
6. Packet definitions
7. BSDL definitions
8. Channel bonding
9. PDL
10. Compliance verification
Annex A (informative) - Bibliography
This standard defines a high speed test access port for delivery of test data, a packet format for describing the test payload, and a distribution architecture for converting the test data to/from on-chip test structures.
| Committee |
Test Technology
|
| DocumentType |
Standard
|
| ISBN |
978-1-5044-3995-4
|
| Pages |
96
|
| PublisherName |
Institute of Electrical & Electronics Engineers
|
| Status |
Current
|
| IEEE 802.3-2012 | IEEE Standard for Ethernet |
| IEEE 1149.1-2013 REDLINE | IEEE Standard for Test Access Port and Boundary-Scan Architecture |
| IEEE 1500:2007 | TESTABILITY METHOD FOR EMBEDDED CORE-BASED INTEGRATED CIRCUITS |
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