GR 78 CORE : ISSUE 2

Preface
1 Introduction
   1.1 Reason for Reissue
   1.2 Organization
   1.3 Requirements Terminology
   1.4 Requirement Labeling Conventions
   1.5 General Criteria
2 Requirements for All Products
   2.1 General
   2.2 Electrical and Mechanical Integrity
   2.3 Administration of Requirements
3 Materials and Finishes Requirements
   3.1 General
   3.2 Materials
   3.3 Finishes
4 Separable Connector Requirements
   4.1 General
   4.2 Two-part and PWB Edge Card Connectors
   4.3 Component Sockets
   4.4 Insulation Displacement Connectors
   4.5 Zero Insertion Force Connectors
   4.6 Coaxial Connectors
   4.7 Optical Connectors
5 Wire and Cable Requirements
   5.1 Metallic Wire and Cable
   5.2 Optical Fiber and Optical Fiber Cables
6 Printed Wiring Board Requirements
   6.1 General
   6.2 Multilayer PWBs - General Requirements
   6.3 Printed Wiring Boards for Surface Mounting
   6.4 Printed Wiring Boards for Backpanels
   6.5 Encapsulated Discrete Wire Interconnection Boards
7 PWB Assembly Requirements
   7.1 General
   7.2 PWB Assemblies - Through-hole Mounted Components
   7.3 PWB Assemblies - Surface Mounted Components
   7.4 Backpanel PWB Assemblies
8 Equipment Sub-Assembly and Assembly Requirements
   8.1 General
   8.2 Manufacturing
   8.3 Equipment Modifications
   8.4 Performance
9 Electrostatic Discharge
   9.1 General
   9.2 Susceptibility
   9.3 ESD Resistance
   9.4 Circuit Pack ESD Test Methods and Requirements
   9.5 ESD Warning Label Requirements
10 Product Identification and Markings Requirements
11 Package Requirements
12 Repair and Modification of Customer Return Units
   12.1 General
   12.2 Marking
   12.3 Repairs
13 Qualification Test Procedures
   13.1 Corrosiveness of Soldering Fluxes
   13.2 Polymeric Coatings and Adhesive Materials
   13.3 Separable Connector and Socketed Component
        Lubricant Qualification
   13.4 Qualification Test Procedures for Lap Soldered
        Modification Wires to PWB Assemblies
   13.5 Qualification of Additive Circuitry for Bare
        PWB Modifications
14 Tests and Methods
   14.1 General
   14.2 Metal Finishes
   14.3 PWBs
   14.4 Insulation Resistance Testing
   14.5 Solvent Extract Conductivity Testing
Glossary
References
List of Figures
14-1 Standard Insulation Resistance Test Pattern
14-2 Striped Solder Mask Coated Standard Test Pattern
14-3 Solder Mask Coated Standard Test Pattern
14-4 Simplified Schematic of the ESD Simulator
14-5 Theoretical Waveform
14-6 Discharge Electrode and Resistive Current Monitor
14-7 Waveform Monitor Using a Current Probe
14-8 Pictorial Schematic of Test Procedure
14-9 Logo for ESD Sensitive Equipment
14-10 Logo for ESD Protected Area
14-11 Etched Copper (a matrix of pads) on the Bottom
      Layer (the 6 sets of lines are labelled A through F)
14-12 Added Conductor Providing Daisy Chain Continuity
      Between the Pads Modification of A, B, C and D
      Circuitry
14-13 Added Conductor for Insulation Integrity Measurement
      Modification of E and F lines
List of Tables
4-1 Noble Metallizations Thicknesses - Excluding
     PWB Contact Fingers
4-2 Noble Metallizations Thicknesses - PWB Contact
     Fingers
4-3 Lubricants for Contacts with Noble Metallizations
4-4 Lubricants for Contacts with Base Metallizations
5-1 Outside Plant Cable Requirements
5-2 Outside Plant Wire Requirements
5-3 Customer Premises Wire and Cable Requirements
5-4 Central Office Wire and Cable Requirements
5-5 Minimum Torques
6-1 Requirements by PWB Type
6-2 8-Layer Multilayer Structure (Example Only)
6-3 8-Layer Multilayer Layup (Example Only)
8-1 Turns Required for Solderless Wrapped Connections
8-2 Strip-Off Forces for Solderless Wrapped Connections
9-1 Verification Parameters for a Bodyfinger ESD
     Waveform into a Short
9-2 Verification Parameters for a Bodyfinger ESD
     (Into a 500-omega Resistor
13-1 Sample Preparation - Liquid Fluxes
13-2 Sample Preparation - Solder Pastes
13-3 Sample Preparation - Cored Solder Wire
13-4 Minimum Insulation Resistance Values
13-5 Tests Required for Polymeric and Adhesive Materials
13-6 Values of IRmin vs. Pattern Spacing
14-1 Typical Pore Counts for Electrographic Porosity
     Test
14-2 Insulation Resistance Test Pattern Requirements
14-3 Summary of Insulation Resistance Requirements
14-4 Summary of Contamination Limits

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