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IEC 60191-6-5:2001

Current

Current

The latest, up-to-date edition.

Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)

Available format(s)

Hardcopy , PDF , PDF 3 Users , PDF 5 Users , PDF 9 Users

Language(s)

English, Spanish, Castilian

Published date

08-27-2001

US$46.00
Excluding Tax where applicable

FOREWORD
1 Scope
2 Normative references
3 Definitions
Tables

Provides common outline drawings and dimensions for all types of structures and composed materials of fine-pitch ball grid array the terminal pitch of which is less than or equal to 0,80 mm.

DevelopmentNote
Also numbered as BS EN 60191-6-5. (12/2001) Stability Date: 2020. (10/2012)
DocumentType
Standard
Pages
10
PublisherName
International Electrotechnical Committee
Status
Current

CEI EN 60191-6-17 : 2012 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-17: GENERAL RULES FOR THE PREPARATION OF OUTLINE DRAWINGS OF SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGES - DESIGN GUIDE FOR STACKED PACKAGES - FINE-PITCH BALL GRID ARRAY AND FINE-PITCH LAND GRID ARRAY (P-PFBGA AND P-PFLGA)
BS EN 60191-6-18:2010 Mechanical standardization of semiconductor devices General rules for the preparation of outline drawings of surface mounted semiconductor device packages. Design guide for ball grid array (BGA)
I.S. EN 60191-6-17:2011 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-17: GENERAL RULES FOR THE PREPARATION OF OUTLINE DRAWINGS OF SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGES - DESIGN GUIDE FOR STACKED PACKAGES - FINE-PITCH BALL GRID ARRAY AND FINE-PITCH LAND GRID ARRAY (P-PFBGA AND P-PFLGA)
EN 60191-6-18:2010 Mechanical standardization of semiconductor devices - Part 6-18: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for ball grid array (BGA)
EN 60191-6-17:2011 Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)
EN 62137:2004/corrigendum:2005 ENVIRONMENTAL AND ENDURANCE TESTING - TEST METHODS FOR SURFACE-MOUNT BOARDS OF AREA ARRAY TYPE PACKAGES FBGA, BGA, FLGA, LGA, SON AND QFN
BS EN 60191-6-19:2010 Mechanical standardization of semiconductor devices Measurement methods of the package warpage at elevated temperature and the maximum permissible warpage
NF EN 60191-6-19 : 2010 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-19: MEASUREMENT METHODS OF PACKAGE WARPAGE AT ELEVATED TEMPERATURE AND THE MAXIMUM PERMISSIBLE WARPAGE
IEC PAS 60191-6-18:2008 Mechanical standardization of semiconductor devices - Part 6-18: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for ball grid array (BGA)
IEC 62137:2004 Environmental and endurance testing - Test methods for surface-mount boards of area array type packages FBGA, BGA, FLGA, LGA, SON and QFN
BS EN 62137:2004 Environmental and endurance testing. Test methods for surface-mount boards of area array type packages FBGA, BGA, FLGA, LGA, SON and QFN
CEI EN 60191-6-18 : 2011 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-18: GENERAL RULES FOR THE PREPARATION OF OUTLINE DRAWINGS OF SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGES - DESIGN GUIDE FOR BALL GRID ARRAY (BGA)
CEI EN 60191-6-22 : 2014 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-22: GENERAL RULES FOR THE PREPARATION OF OUTLINE DRAWINGS OF SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGES - DESIGN GUIDE FOR SEMICONDUCTOR PACKAGES SILICON FINE-PITCH BALL GRID ARRAY AND SILICON FINE-PITCH LAND GRID ARRAY (S-FBGA AND S-FLGA)
I.S. EN 60191-6-18:2010 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-18: GENERAL RULES FOR THE PREPARATION OF OUTLINE DRAWINGS OF SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGES - DESIGN GUIDE FOR BALL GRID ARRAY (BGA)
IEC 60191-6-18:2010 Mechanical standardization of semiconductor devices - Part 6-18: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for ball grid array (BGA)
IEC 62137-4:2014 Electronics assembly technology - Part 4: Endurance test methods for solder joint of area array type package surface mount devices
BS EN 60191-6-17:2011 Mechanical standardization of semiconductor devices General rules for the preparation of outline drawings of surface mounted semiconductor device packages. Design guide for stacked packages. Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)
I.S. EN 62137:2005 ENVIRONMENTAL AND ENDURANCE TESTING - TEST METHODS FOR SURFACE-MOUNT BOARDS OF AREA ARRAY TYPE PACKAGES FBGA, BGA, FLGA, LGA, SON AND QFN
CEI EN 60191-6-19 : 2011 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-19: MEASUREMENT METHODS OF THE PACKAGE WARPAGE AT ELEVATED TEMPERATURE AND THE MAXIMUM PERMISSIBLE WARPAGE
IEC 60191-6-17:2011 Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)
IEC 60191-6-19:2010 Mechanical standardization of semiconductor devices - Part 6-19: Measurement methods of the package warpage at elevated temperature and the maximum permissible warpage
EN 60191-6-22:2013 Mechanical standardization of semiconductor devices - Part 6-22: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for semiconductor packages Silicon Fine-pitch Ball Grid Array and Silicon Fine-pitch Land Grid Array (S-FBGA and S-FLGA)
BS EN 62137-4:2014 Electronics assembly technology Endurance test methods for solder joint of area array type package surface mount devices
I.S. EN 62137-4:2014 ELECTRONICS ASSEMBLY TECHNOLOGY - PART 4: ENDURANCE TEST METHODS FOR SOLDER JOINT OF AREA ARRAY TYPE PACKAGE SURFACE MOUNT DEVICES
BS EN 60191-6-22:2013 Mechanical standardization of semiconductor devices General rules for the preparation of outline drawings of surface mounted semiconductor device packages. Design guide for semiconductor packages Silicon Fine-pitch Ball Grid Array and Silicon Fine-pitch Land Grid Array (S-FBGA and S-FLGA)
07/30155531 DC : 0 BS EN 60191-6-17 - MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-17: DESIGN GUIDE FOR STACKED PACKAGES AND INDIVIDUAL STACKABLE PACKAGES - FINE-PITCH BALL GRID ARRAY AND FINE-PITCH LAND GRID ARRAY PACKAGES (FBGA/FLGA)
I.S. EN 60191-6-22:2013 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-22: GENERAL RULES FOR THE PREPARATION OF OUTLINE DRAWINGS OF SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGES - DESIGN GUIDE FOR SEMICONDUCTOR PACKAGES SILICON FINE-PITCH BALL GRID ARRAY AND SILICON FINE-PITCH LAND GRID ARRAY (S-FBGA AND S-FLGA) (IEC 60191-6-22:2012 (EQV))
I.S. EN 60191-6-19:2010 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-19: MEASUREMENT METHODS OF THE PACKAGE WARPAGE AT ELEVATED TEMPERATURE AND THE MAXIMUM PERMISSIBLE WARPAGE
IEC 60191-6-22:2012 Mechanical standardization of semiconductor devices - Part 6-22: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for semiconductor packages Silicon Fine-pitch Ball Grid Array and Silicon Fine-pitch Land Grid Array (S-FBGA and S-FLGA)
EN 60191-6-19:2010 Mechanical standardization of semiconductor devices - Part 6-19: Measurement methods of the package warpage at elevated temperature and the maximum permissible warpage
EN 62137-4:2014/AC:2015 ELECTRONICS ASSEMBLY TECHNOLOGY - PART 4: ENDURANCE TEST METHODS FOR SOLDER JOINT OF AREA ARRAY TYPE PACKAGE SURFACE MOUNT DEVICES (IEC 62137-4:2014)

IEC 60191-6:2009 Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages

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